EENG 484 - Advanced Digital Design

Date Lesson Topic Assigned
Aug 24 (M) L1 Symbolic to VHDL, entity architecture, std_logic, signals  
Aug 26 L2 TT to VHDL, Literals, Vectors, Don't cares Homework 1
Aug 28 L3 Generics, Basic Building Block, Entity and Architecture Homework 2
Aug 31 (M) L4 Sequential Building Blocks Homework 3
Sept 2 L5 Libraries, Testbench Homework 4
Sept 4 L6 Design of enhanced PWM for lab 1  
Sept 7(M)   Labor Day  
Sept 9 Lab 1 Enhanced PWM Lab 1
Sept 11 L9 VHDL Synthesis - Porting PWM to PL in Zynq  
Sept 14 L10 VGA Standard Homework 5
Sept 16   Career Day  
Sept 18 L11 Design of VGA to HDMI for lab 02  
Sept 21 (M) Lab 2 VGA to HDMI
Sept 23 Lab 2 VGA to HDMI
Sept 25 Lab 2 VGA to HDMI Lab 2
Sept 28 (M) L15 Datapath and control architecture and timing  
Sept 30 L16 Stopwatch Control Unit in VHDL Homework 6
Oct 2 L17 Stopwatch Datapath in VHDL Homework 7
Oct 5 (M) L18 Exam Review Homework 8
Oct 7   Exam  
Oct 9 L20 AD7606 chip, Input, Output and Behavior  
Oct 12 (M)   Fall Break  
Oct 14 L21 Design of datapath and control for Lab 3  
Oct 16 L22 Design of datapath and control for Lab 3  
Oct 19 (M) Lab 3 Acquire
Oct 21 Lab 3 Acquire
Oct 23 Lab 3 Acquire Lab 3
Oct 26 (M) L26 BRAM, IP I/O and Behavior  
Oct 28 L27 Design of datapath and control for Lab 4  
Oct 30 L28 Design of datapath and control for Lab 4  
Nov 2 (M) Lab 4 acquireToDisplay
Nov 4 Lab 4 acquireToDisplay
Nov 6 Lab 4 acquireToDisplay  
Nov 9 (M) Lab 4 acquireToDisplay Lab 4
Nov 11 L32 Building Custom IP  
Nov 13 L33 Design of enhancedPWM with Zynq for Lab 5  
Nov 16 (M) Lab 5 enhancedPWM with Zynq
Nov 18 Lab 5 enhancedPWM with Zynq Lab 5
Nov 20 L37 Design of acquireToHdmi with Zynq for Lab 6  
Nov 23-27   Thanksgiving  
Nov 30 (M) Lab 6 acquireToHdmi with Zynq
Dec 1 Lab 6 acquireToHdmi with Zynq
Dec 3 Lab 6 acquireToHdmi with Zynq
Dec 7 (M) Lab 6 acquireToHdmi with Zynq
Dec 9 Lab 6 acquireToHdmi with Zynq Lab 6