Aug 25 (M) |
L1 |
Symbolic to VHDL, entity architecture, std_logic, signals |
|
Aug 27 |
L2 |
TT to VHDL, Literals, Vectors, Don't cares |
Homework 1 |
Aug 29 |
L3 |
Generics, Basic Building Block, Entity and Architecture |
Homework 2 |
Sept 3 |
L4 |
Sequential Building Blocks |
Homework 3 |
Sept 5 |
L5 |
Libraries, Testbench |
Homework 4 |
Sept 8 (M) |
L6 |
Design of enhanced PWM for lab 1 |
|
Sept 10 |
Lab 1 |
Enhanced PWM |
Sept 12 |
Lab 1 |
Enhanced PWM |
Lab 1 |
Sept 15(M) |
L9 |
VHDL Synthesis - Porting PWM to PL in Zynq |
|
Sept 19 |
L10 |
VGA Standard |
Homework 5 |
Sept 22 (M) |
L11 |
Design of VGA to HDMI for lab 02 |
  |
Sept 24 |
Lab 2 |
VGA to HDMI |
Sept 26 |
Lab 2 |
VGA to HDMI |
Sept 29 (M) |
Lab 2 |
VGA to HDMI |
Lab 2 |
Oct 1 |
L15 |
Datapath and control architecture and timing |
|
Oct 3 |
L16 |
Stopwatch Control Unit in VHDL |
Homework 6 |
Oct 6 (M) |
L17 |
Stopwatch Datapath in VHDL |
Homework 7 |
Oct 8 |
L18 |
Exam Review |
Homework 8 |
Oct 10 |
Exam |
Oct 13 (M) |
L20 |
AD7606 chip, Input, Output and Behavior |
  |
Oct 15 |
L21 |
Design of datapath and control for Lab 3 |
  |
Oct 17 |
L22 |
Design of datapath and control for Lab 3 |
  |
Oct 22 |
Lab 3 |
Acquire |
Oct 24 |
Lab 3 |
Acquire |
Oct 27 (M) |
Lab 3 |
Acquire |
Lab 3 |
Oct 29 |
L26 |
BRAM, IP I/O and Behavior |
  |
Oct 31 |
L27 |
Design of datapath and control for Lab 4 |
  |
Nov 3 (M) |
L28 |
Design of datapath and control for Lab 4 |
  |
Oct 5 |
Lab 4 |
acquireToDisplay |
Nov 7 |
Lab 4 |
acquireToDisplay |
Nov 10 (M) |
Lab 4 |
acquireToDisplay |
Lab 4 |
Nov 12 |
L32 |
Building Custom IP |
  |
Nov 14 |
L33 |
Programming Custom IP |
  |
Nov 17 (M) |
Lab 5 |
enhancedPWM with Zynq |
Nov 19 |
Lab 5 |
enhancedPWM with Zynq |
Nov 21 |
Lab 5 |
enhancedPWM with Zynq |
Lab 5 |
Dec 1 (M) |
L37 |
Design of acquireToHdmi with Zynq for Lab 6 |
  |
Dec 3 |
Lab 6 |
acquireToHdmi with Zynq |
Dec 5 |
Lab 6 |
acquireToHdmi with Zynq |
Dec 8 (M) |
Lab 6 |
acquireToHdmi with Zynq |
Dec 10 |
Lab 6 |
acquireToHdmi with Zynq |
Lab 6 |